Commented dissassembly of the KC compact operating system rom
;; identical to English CPC6128 operating system rom up to this point
;; initialise crtc
;; table of data
05a1 21e505 ld hl,$05e5
;; initialise registers backwards
05a4 010fbc ld bc,$bc0f
05a7 ed49 out (c),c
05a9 2b dec hl
05aa 7e ld a,(hl)
05ab 04 inc b
05ac ed79 out (c),a
05ae 05 dec b
05af 0d dec c
05b0 f2a705 jp p,$05a7
05b3 3100c0 ld sp,$c000
05b6 06f5 ld b,$f5 ;; 8255 ppi port B
05b8 ed78 in a,(c)
05ba 1f rra
05bb 1f rra
05bc 21b106 ld hl,$06b1 ;; start of Z8536 configuration data
05bf 013dee ld bc,$ee3d ;; Z8536 control register port &eexx, and Z8536 setup count for operating system
05c2 3005 jr nc,$05c9 ;; /TEST=0
05c4 cda206 call $06a2
05c7 181c jr $05e5 ;; /TEST=1
;; continue OS start-up
05c9 cda006 call $06a0 ;; initialise Z8536 for test program transfer
05cc 2180a8 ld hl,$a880 ;; transfer test program to &a880
05cf 1e00 ld e,$00
05d1 e5 push hl
05d2 c33807 jp $0738
;; crtc data identical to crtc data for 50hz display in English CPC6128
;; operating system rom (but moved from 0x05c5)
;; 0x05d5
defb &3f, &28, &2e, &8e, &26, &00, &19, &1e, &00, &07, &00, &00,&30, &00
defb &c0, &00
;; range 0x05e5-0x067c
;; identical to English CPC6128 operating system rom
067d 218206 ld hl,$0682 ;; start up string
0680 1879 jr $06fb ;; display start up string
;; "KC Compact Version 1.3"
;; &682-&69f
defb &0a,"KC Compact",&0d,&0a," Version 1.3",0x0d,0x0a,0x00,0x00
;; setup Z8536
06b1
05bf 013dee ld bc,$ee3d
;; starts here when initialise Z8536 for test program transfer
06a0 0e31 ld c,$31
;; starts here when initialise Z8536 for operating system start-up
;; reset Z8536 state (Z8536 is in reset state)
06a2 ed78 in a,(c)
;; Z8536 go to state 0 (Z8536 is now waiting for register index write)
06a4 af xor a
06a5 ed79 out (c),a
06a7 ed78 in a,(c)
;; loop now does: write register index, write register data, write register index,.....
06a9 7e ld a,(hl)
06aa ed79 out (c),a ; write register index or register data
06ac 23 inc hl
06ad 0d dec c
06ae 20f9 jr nz,$06a9
06b0 c9 ret
;; 0x06b1
;; start of Z8536 configuration data
defb &00, &01 ;; Master interrupt control: reset
;; at this point, Z8536 is in reset state, and requires a write with bit 0=0
;; a read will not change it's state.
defb &22 ;; advance CIO to state 0 from RESET STATE
defb &2a, &44 ;; Port B's data path polarity: 01000100 (invert bits 2 and 6)
defb &05, &02 ;; Port C's data path polarity: 00000000 (do not invert any bits)
defb &23, &bd ;; Port A's data direction: 10111101 (bit 1 is INPUT, bit 6 is INPUT all other bits are OUTPUT)
defb &2b, &ee ;; Port B's data direction: 11101110 (bit 0 is INPUT, bit 4 is INPUT all other bits are OUTPUT)
defb &06, &ee ;; Port C's data direction: 11101110 (bit 0 is INPUT, bit 4 is INPUT all other bits are OUTPUT)
defb &24, &42 ;; Port A's special I/O Control
defb &0d, &ff ;; Port A's data: 11111111
defb &01, &94 ;; Master Configuration Control: Port B enable, disable counters, port a enable
defb &16, &02 ;; Counter/Timer 1's Time Constant MSB: &02
defb &17, &47 ;; Counter/Timer 1's Time Constant LSB: &47
defb &18, &01 ;; Counter/Timer 2's Time Constant MSB: &01
defb &19, &67 ;; Counter/Timer 2's Time Constant LSB: &67
defb &1a, &00 ;; Counter/Timer 3's Time Constant MSB: &00
defb &1b, &1a ;; Counter/Timer 3's Time Constant LSB: &1a
;; Timer 1 time constant: &0247 (583), Timer 2 time constant: &0167 (359), Timer 3 time constant: &1a (26 = 52 * (1/2)!!!!)
defb &1c, &fc ;; Counter/Timer 1's Mode specification: Continuous,external output enable,external count enable,
;; external trigger enable, external gate enable, retrigger enable bit, pulse output
defb &1d, &fc ;; Counter/Timer 2's Mode specification: Continuous,external output enable,external count enable,
;; external trigger enable, external gate enable, retrigger enable bit, pulse output
defb &1e, &fc ;; Counter/Timer 3's Mode specification: Continuous,external output enable,external count enable,
;; external trigger enable, external gate enable, retrigger enable bit, pulse output
defb &0a, &04 ;; Counter/Timer 1's Command and Status: Gate Command Bit
defb &0b, &04 ;; Counter/Timer 2's Command and Status: Gate Command Bit
defb &0c, &04 ;; Counter/Timer 3's Command and Status: Gate Command Bit
defb &01, &f4 ;; Master Configuration Control: Port B enable, Counter/Timer 1 enable, Counter/Timer 2 enable,
;; Counter/Timer 3 enable, port A and B operate independantly, port A enable, counter/timers are
;; idependant
defb &0a, &06 ;; Counter/Timer 1's Command and Status: Gate Command Bit,Trigger Command Bit
defb &0b, &06 ;; Counter/Timer 2's Command and Status: Gate Command Bit,Trigger Command Bit
;; the following are setup for the operating system only
defb &01, &f0 ;; Master Configuration Control: Port B enable, Counter/Timer 1 enable, Counter/Timer 2 enable,
;; Counter/Timer 3 enable, port A and B operate independantly, port A disable, counter/timers are
;; idependant
defb &22, &80 ;; Port A's data path polarity: invert bit 7, all other bits unchanged
defb &23, &00 ;; Port A's data direction: all bits output
defb &24, &00 ;; Port A's special I/O control: no actions
defb &01, &f4 ;; Master Configuration Control: Port B enable, Counter/Timer 1 enable, Counter/Timer 2 enable,
;; Counter/Timer 3 enable, port A and B operate independantly, port A enable, counter/timers are
;; idependant
defb &0d, &7f ;; Port A's data: 01111111 (/strobe = 0)
;; end of Z8536 configuration data
;; write 0x0ff - DATA1="1", DATA2="1", /STROBE="1", DATA7="1"
06ee 0eff ld c,$ff
06f0 ed49 out (c),c
06f2 ed78 in a,(c)
06f4 17 rla ;; carry contains state of /STROBE
06f5 30f9 jr nc,$06f0
;; to get here /STROBE must read as "1"
06f7 1873 jr $076c ;; wait
;; range 0x06f9-0x0722
;; identical to English CPC6128 operating system rom
0723 212707 ld hl,$0727
0726 c9 ret
;; "Ams",0
;; 0x0727
defb "Ams"",0
;; get data bit
072b ed78 in a,(c)
072d 17 rla ;; carry contains state of /STROBE
072e d4ee06 call nc,$06ee ;; if strobe is 0, write 0x0ff and wait for /STROBE to change to 1
0731 1f rra
0732 1f rra ;; carry contains state of DATA1
;; write 0x0f and wait
0733 0e0f ld c,$0f
0735 1833 jr $076a
0737 c9 ret
;; transfer test program sequence
0738 06ef ld b,$ef ;; transfer using printer port
;; printer port DATA2, DATA1, /STROBE and DATA7
;; are also available on the expansion port
;; synchronisation stage
073a ed78 in a,(c) ;; state of /STROBE
073c 17 rla ;; carry contains state of /STROBE
073d 30fb jr nc,$073a
;; to get here /STROBE must read as "1"
073f 1f rra
0740 1f rra ;; carry contains state of DATA1
0741 30f7 jr nc,$073a
;; to get here /STROBE and DATA1 must read as "1"
0743 ed78 in a,(c)
0745 17 rla ;; carry contains state of /STROBE
0746 30f2 jr nc,$073a
;; to get here /STROBE must read as "1"
0748 1f rra
0749 1f rra ;; carry contains state of DATA1
074a 38f7 jr c,$0743
;; to get here /STROBE must read as "1" and DATA1 must read as "0"
074c cd3307 call $0733 ;; write 0x0f and wait (DATA1="1", DATA2="1",DATA7="0", /STROBE="0")
;; repeat 8 times (once for each bit)
074f 1608 ld d,$08
0751 cdee06 call $06ee ;; write 0x0ff and wait for /STROBE to change to 1
;; DATA1="1", DATA2="1",DATA7="1"/STROBE="1"
0754 cd2b07 call $072b ;; read bit
0757 cb16 rl (hl) ;; shift data bit in
0759 15 dec d
075a 20f5 jr nz,$0751
075c 0ef0 ld c,$f0
075e cdf006 call $06f0 ;; write 0x0f0 and wait
;; DATA1="0", DATA2="0",DATA7="1",/STROBE="1"
0761 cd2b07 call $072b ;; get data bit
0764 23 inc hl
0765 1d dec e
0766 2886 jr z,$06ee ;; if 256 bytes have been transfered...
0768 18e5 jr $074f
;; write and wait
076a ed49 out (c),c
;; wait
076c f5 push af
076d 3e11 ld a,$11
076f 3d dec a
0770 20fd jr nz,$076f
0772 f1 pop af
0773 c9 ret
0774 00 nop
;; range 0x0775-0x03fff
;; identical to English CPC6128 operating system rom
Dissassembly made using dZ80 tool by Mark Incley