;; program 2 org &8000 ;; disable interrupts di ;; unlock asic to gain access to asic registers ld b,&bc ld hl,sequence ld e,17 .seq ld a,(hl) out (c),a inc hl dec e jr nz,seq ;; page-in asic registers ld bc,&7fb8 out (c),c ;; wait for end of vsync ;; I use this so I can predict when the next raster interrupt will occur ;; In the CPC and CPC+ design a raster interrupt is triggered on the second HSYNC after the ;; the start of the VSYNC signal. ld b,&f5 .l1 in a,(c) rra jr nc,l1 .l2 in a,(c) rra jr c,l2 ;; set interrupt mode 0 im 0 ld hl,&4030 ;; dma instruction "issue interrupt request and stop executing dma list" ld (&9000),hl ld hl,&9000 ld (&6c04),hl ;; set dma channel 1 address (source of dma instruction list for channel 1) ld a,0 ld (&6c06),a ;; set dma channel 1 prescalar ld a,&20 ld (&6805),a ;; set interrupt vector ;; clear raster counter (has the effect of forcing next raster interrupt to not ;; occur closer than 52-HSYNCs). ld bc,&7f00+%10011100 out (c),c ld a,%00000010 ;; enable dma channel 1, first instruction will execute on the next HSYNC ld (&6c0f),a ;; page-out asic registers ld bc,&7fa0 out (c),c ;; enable interrupts ei ;; wait for interrupt to occur halt ;; "dummy" instructions ld d,h ld e,l di ;; disable interrupts so we can change interrupt mode safely im 1 ;; set Z80 interrupt mode 1 (see comment for "BRK" below) brk ;; this is a special instruction provided by the Maxam assembler/dissassembler/monitor ;; when executed a dump of the register values is displayed. This instruction assembles ;; to a RST 30H. This instruction uses the Amstrad firmware to execute, and the Amstrad ;; firmware requires interrupt mode 1. ;; this is the sequence to unlock the ASIC extra features .sequence defb &ff,&00,&ff,&77,&b3,&51,&a8,&d4,&62,&39,&9c,&46,&2b,&15,&8a,&cd,&ee