Dynamic RAM Refresh

Refresh means you stimulate the DRAM to prevent "vaporization" (loss) of data due to leakage current in the microcondensers that constitute the bits (the bits are internally rewritten at once even when addressed for reading).

Inside a DRAM chip, each bit plane is arranged in a usually square array of microcondensers and transistors, and not real registers (as in static RAM) because it is 3 times bigger and draws 100 times more power.

To access a bit in the matrix, you split the address in two halves: one for the row, the other for the column. On the side of the matrix, there are "binary-to-unary" converters, big gates that convert a k bit number n into a "token" on the nth of its 2 k output lines. One is called the "row selector", the other is the "column selector".

To understand the process of refresh, look at Reads and Writes: the row selector sends its token to all the bits in the selected row. The transistor in each bit will recieve it and close a circuit that comprises the condenser and goes to the side of the matrix through 2 vertical lines for each column (these lines are shared between all the bits in the column, but only one row has the token so we don't care for the others).

On the other end of the lines, there is a feedback circuit: a transistor that will be triggered if the potential of the condenser is over a threshold (the bit is 1) and will re-saturate it only in this case: it is refreshed, and all the bits in the row are refreshed simultaneously (actually, this logic is rather in the middle of the matrix than on the side, to minimize propagation delay).

Now, we made this access for some other reason: to read or write. Reading is easy: every feedback transistor on the matrix side also sends current into an AND gate (for each column, the other input of the gate being the lines with the column selection token...). Now all the AND gates are dumped into a giant OR, which is the value read at the address (well, may be add one last amplifier for security...)

Writing is a little more complex: it depends on the bit you want to write. If it is a 1, a trick is to have the feedback transistor trigger even if the matrix bit has its condenser under threshold. For that reason, this transistor is actually triggered by an OR between the matrix bit and the value to write for that column, which is an AND of the bit to write and the column token line .... huh ? Look at the pictures, it'll be better !

If you want to write a 0, it gets even more complicated: instead of routing the matrix bit to a feedback circuit, you route it to a resistor to discharge the condenser (but only in the right column please !)

[General Layout]

[Image shows general Layout of a dynamic RAM]

[A Matrix Element]

[Image shows one element of the matrix used to store the data bit values]

[Refresh Logic]

[Image shows the Dynamic RAM refresh logic]

[Column Select Logic]

[Image shows the Column Select logic to select a data bit in the Dynamic RAM]

A popular 4*16kbit DRAM like those used in the CPCs, is made of 4 matrixes of 128*128 entries. So there are 27 rows to refresh as often as possible because microcondensers are not reliable after a few miliseconds.

The real function of the refresh (R) register in the Z80 is to tell what row to refresh. It is taylored for 16kbit DRAMs: each tick the Z80 fetches an instruction byte, it increments R, and the next cycle, it will raise its "refresh" pin to tell the other chips to leave the Address Bus (AB) alone, and put R on the lower 7 bits of AB, and all RAMs will see this row refreshed. The other bits of AB are undefined, we only need to select a row as a whole to refresh it.

During HALTs, the Z80 actually generates virtual fetches of NOPs to keep on refreshing the RAM. As a consequence, a HALT can only last for an integer number of NOP cycles (on all Z80 machines).

(Chips don't need to have their data bus (DB) activated to be refreshed, so they can be refreshed in parallel without any collision problem on DB. Also note that the CPU is always given 2 consecutive ticks to access memory in the CPC architecture, probably for refresh)

This seems very fine, insuring a given row will be refreshed about 7000 times per second. But Zilog made one mistake: they left the R register accessible to the user, which allows him to make very strange hacks with refresh, possibly with disastrous consequences.

On the CPC, the CRTC will act as a backup refresher at least for the lower 64k (I don't know for the rest of the RAM: the banking logic on the expansion board may purely cut the AB when CPU is not using it). The CRTC generates addresses even during retraces that cover up even the few bytes not used by graphics in a regular screen block.

But if you set R0 and R4 to very low values, apart from underscanning and burning your VDU, you will suppress this back up refresh for most of the RAM. (see note)


Custom refreshers

Refresh can also be done by additionnal logic, scanning all the row addresses in a loop. Holding each one for 1 clock tick, refreshing a chip takes 128 ticks. Moreover you have to multiplex refresh with other accesses, so it can stretch to 500 ticks ! This is very long, on a 500Khz baseline device, the duration of the operation is 1 ms, about the same as the periodicity required for it ! Refresh is a neverending complicated task, this is why an integrated refresher was a value point for a chip like the 6845 or the Z80.

On modern (1995) devices, clocks have boosted to 66 Mhz, giving more ticks to multiplex, but DRAMs have up to 4096 rows (16 MB SIMM) so the problem is still the same, although it has become transparent to the end user.

Document written by Pierre Guerrier.